soc: st: stm32: stm32g0x: enable ART flash cache accelerator #72971
Conversation
This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. To review, open the file in an editor that reveals hidden Unicode characters.
Learn more about bidirectional Unicode characters
zephyrbot
requested review from
ajarmouni-st,
erwango,
FRASTM,
gautierg-st and
GeorgeCGV
Enable instruction cache and prefetching on STM32G0X SoC family. Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
erwango
approved these changes
May 20, 2024
FRASTM
approved these changes
May 23, 2024
gautierg-st
approved these changes
May 23, 2024
Sign up for free
to join this conversation on GitHub.
Already have an account?
Sign in to comment
Add this suggestion to a batch that can be applied as a single commit.
This suggestion is invalid because no changes were made to the code.
Suggestions cannot be applied while the pull request is closed.
Suggestions cannot be applied while viewing a subset of changes.
Only one suggestion per line can be applied in a batch.
Add this suggestion to a batch that can be applied as a single commit.
Applying suggestions on deleted lines is not supported.
You must change the existing code in this line in order to create a valid suggestion.
Outdated suggestions cannot be applied.
This suggestion has been applied or marked resolved.
Suggestions cannot be applied from pending reviews.
Suggestions cannot be applied on multi-line comments.
Suggestions cannot be applied while the pull request is queued to merge.
Suggestion cannot be applied right now. Please check back later.
Enable instruction cache and prefetching on STM32G0X SoC family.
This addresses #71417 for that family.