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simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.

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jkeys-ecg-nmsu/cache-simulator-with-coherency

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cache-simulator-with-coherency

This program simulates a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.

Command-line options (formatting for cmd line arguments shamelessly stolen from Prof Jonathan Cook, PhD, NMSU):

  • -b # set the number of words per block (must be a power of 2)
  • -m # set number of cycles per miss (default 2)
  • -n # set number of data words supported in cache (must be a power of 2)
  • -a # set the set-associativity of the cache (must be a power of 2)
  • -c # set the number of cores (each with independent caches that must maintain coherency) (must be a power of 2)
  • -d # enable debugging statements (any non-zero integer)
  • -w 'T' set cache writing policy (K=='T' for write-through or K=='B for write-back)

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simulation of a multi-core (with an arbitrary number of cores) cache, including set associativity, with simple MSI cache coherency.

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