verilog
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XLS: Accelerated HW Synthesis
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Jun 7, 2024 - C++
Single-Cycle CPU for Homework of Computer System Design in CUMT
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Jun 7, 2024 - Verilog
Code generation tool for control and status registers
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Jun 7, 2024 - Ruby
Basic counter example in verilog for Tang Nano 20k using Yosys, Nextpnr and openFPGALoader.
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Jun 7, 2024 - Shell
TX only RoCEv2. Super stripped down version of a RoCEv2 endpoint.
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Jun 7, 2024 - Verilog
Verilator open-source SystemVerilog simulator and lint system
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Jun 7, 2024 - C++
This is my first repo adding to my github account.
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Jun 7, 2024 - C++
Sol-1: A CPU/Computer System made from 74 series logic.
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Jun 7, 2024 - C
An HDL package manager.
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Jun 7, 2024 - Rust
OpenROAD's scripts implementing an RTL-to-GDS Flow. Documentation at https://openroad-flow-scripts.readthedocs.io/en/latest/
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Jun 7, 2024 - Verilog
Examples of SystemC from the High-Level Systems Design course of the Master's Degree in Electronics at the Costa Rica Institute of Technology.
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Jun 7, 2024 - C++
The repository hosts an ongoing project dedicated to the development of an implementation for the Advanced Encryption Standard (AES) 128-bit block cipher in UART communication. Please be advised that this project is currently in progress and subject to updates.
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Jun 7, 2024 - HTML
Veryl: A Modern Hardware Description Language
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Jun 7, 2024 - Rust
BDD Gherkin implementation in native SystemVerilog, based on UVM.
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Jun 7, 2024 - SystemVerilog
This is a SpyDrNet Plugin for a physical design related transformations
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Jun 6, 2024 - Python
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