Failed to to build test

[JunChi1022]

When i'm trying to build the tests, i meet following errors. It seems that there are syntax error in the verilog codes

iverilog -o build/sim.vvp -s gpu -g2012 build/gpu.v
build/gpu.v:187: error: Port data_mem_read_data of module core is declared as input and as a reg type.
build/gpu.v:186: error: Port data_mem_read_ready of module core is declared as input and as a reg type.
build/gpu.v:191: error: Port data_mem_write_ready of module core is declared as input and as a reg type.
build/gpu.v:183: error: Port program_mem_read_data of module core is declared as input and as a reg type.
build/gpu.v:182: error: Port program_mem_read_ready of module core is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:641: error: Port core_state of module fetcher is declared as input and as a reg type.
build/gpu.v:642: error: Port current_pc of module fetcher is declared as input and as a reg type.
build/gpu.v:646: error: Port mem_read_data of module fetcher is declared as input and as a reg type.
build/gpu.v:645: error: Port mem_read_ready of module fetcher is declared as input and as a reg type.
build/gpu.v:441: error: Port core_state of module decoder is declared as input and as a reg type.
build/gpu.v:442: error: Port instruction of module decoder is declared as input and as a reg type.
build/gpu.v:1143: error: Port decoded_mem_read_enable of module scheduler is declared as input and as a reg type.
build/gpu.v:1144: error: Port decoded_mem_write_enable of module scheduler is declared as input and as a reg type.
build/gpu.v:1145: error: Port decoded_ret of module scheduler is declared as input and as a reg type.
build/gpu.v:1146: error: Port fetcher_state of module scheduler is declared as input and as a reg type.
build/gpu.v:1147: error: Port lsu_state of module scheduler is declared as input and as a reg type.
build/gpu.v:1149: error: Port next_pc of module scheduler is declared as input and as a reg type.
build/gpu.v:187: error: Port data_mem_read_data of module core is declared as input and as a reg type.
build/gpu.v:186: error: Port data_mem_read_ready of module core is declared as input and as a reg type.
build/gpu.v:191: error: Port data_mem_write_ready of module core is declared as input and as a reg type.
build/gpu.v:183: error: Port program_mem_read_data of module core is declared as input and as a reg type.
build/gpu.v:182: error: Port program_mem_read_ready of module core is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:1235: error: Port core_state of module alu is declared as input and as a reg type.
build/gpu.v:1236: error: Port decoded_alu_arithmetic_mux of module alu is declared as input and as a reg type.
build/gpu.v:1237: error: Port decoded_alu_output_mux of module alu is declared as input and as a reg type.
build/gpu.v:1238: error: Port rs of module alu is declared as input and as a reg type.
build/gpu.v:1239: error: Port rt of module alu is declared as input and as a reg type.
build/gpu.v:922: error: Port core_state of module lsu is declared as input and as a reg type.
build/gpu.v:923: error: Port decoded_mem_read_enable of module lsu is declared as input and as a reg type.
build/gpu.v:924: error: Port decoded_mem_write_enable of module lsu is declared as input and as a reg type.
build/gpu.v:930: error: Port mem_read_data of module lsu is declared as input and as a reg type.
build/gpu.v:929: error: Port mem_read_ready of module lsu is declared as input and as a reg type.
build/gpu.v:934: error: Port mem_write_ready of module lsu is declared as input and as a reg type.
build/gpu.v:925: error: Port rs of module lsu is declared as input and as a reg type.
build/gpu.v:926: error: Port rt of module lsu is declared as input and as a reg type.
build/gpu.v:1079: error: Port alu_out of module registers is declared as input and as a reg type.
build/gpu.v:1071: error: Port block_id of module registers is declared as input and as a reg type.
build/gpu.v:1072: error: Port core_state of module registers is declared as input and as a reg type.
build/gpu.v:1078: error: Port decoded_immediate of module registers is declared as input and as a reg type.
build/gpu.v:1073: error: Port decoded_rd_address of module registers is declared as input and as a reg type.
build/gpu.v:1077: error: Port decoded_reg_input_mux of module registers is declared as input and as a reg type.
build/gpu.v:1076: error: Port decoded_reg_write_enable of module registers is declared as input and as a reg type.
build/gpu.v:1074: error: Port decoded_rs_address of module registers is declared as input and as a reg type.
build/gpu.v:1075: error: Port decoded_rt_address of module registers is declared as input and as a reg type.
build/gpu.v:1080: error: Port lsu_out of module registers is declared as input and as a reg type.
build/gpu.v:1018: error: Port alu_out of module pc is declared as input and as a reg type.
build/gpu.v:1013: error: Port core_state of module pc is declared as input and as a reg type.
build/gpu.v:1019: error: Port current_pc of module pc is declared as input and as a reg type.
build/gpu.v:1015: error: Port decoded_immediate of module pc is declared as input and as a reg type.
build/gpu.v:1014: error: Port decoded_nzp of module pc is declared as input and as a reg type.
build/gpu.v:1016: error: Port decoded_nzp_write_enable of module pc is declared as input and as a reg type.
build/gpu.v:1017: error: Port decoded_pc_mux of module pc is declared as input and as a reg type.
build/gpu.v:641: error: Port core_state of module fetcher is declared as input and as a reg type.
build/gpu.v:642: error: Port current_pc of module fetcher is declared as input and as a reg type.
build/gpu.v:646: error: Port mem_read_data of module fetcher is declared as input and as a reg type.
build/gpu.v:645: error: Port mem_read_ready of module fetcher is declared as input and as a reg type.
build/gpu.v:441: error: Port core_state of module decoder is declared as input and as a reg type.
build/gpu.v:442: error: Port instruction of module decoder is declared as input and as a reg type.
build/gpu.v:1143: error: Port decoded_mem_read_enable of module scheduler is declared as input and as a reg type.
build/gpu.v:1144: error: Port decoded_mem_write_enable of module scheduler is declared as input and as a reg type.
build/gpu.v:1145: error: Port decoded_ret of module scheduler is declared as input and as a reg type.
build/gpu.v:1146: error: Port fetcher_state of module scheduler is declared as input and as a reg type.
build/gpu.v:1147: error: Port lsu_state of module scheduler is declared as input and as a reg type.
build/gpu.v:1149: error: Port next_pc of module scheduler is declared as input and as a reg type.
build/gpu.v:31: error: Port consumer_read_address of module controller is declared as input and as a reg type.
build/gpu.v:30: error: Port consumer_read_valid of module controller is declared as input and as a reg type.
build/gpu.v:35: error: Port consumer_write_address of module controller is declared as input and as a reg type.
build/gpu.v:36: error: Port consumer_write_data of module controller is declared as input and as a reg type.
build/gpu.v:34: error: Port consumer_write_valid of module controller is declared as input and as a reg type.
build/gpu.v:41: error: Port mem_read_data of module controller is declared as input and as a reg type.
build/gpu.v:40: error: Port mem_read_ready of module controller is declared as input and as a reg type.
build/gpu.v:45: error: Port mem_write_ready of module controller is declared as input and as a reg type.
build/gpu.v:31: error: Port consumer_read_address of module controller is declared as input and as a reg type.
build/gpu.v:30: error: Port consumer_read_valid of module controller is declared as input and as a reg type.
build/gpu.v:35: error: Port consumer_write_address of module controller is declared as input and as a reg type.
build/gpu.v:36: error: Port consumer_write_data of module controller is declared as input and as a reg type.
build/gpu.v:34: error: Port consumer_write_valid of module controller is declared as input and as a reg type.
build/gpu.v:41: error: Port mem_read_data of module controller is declared as input and as a reg type.
build/gpu.v:40: error: Port mem_read_ready of module controller is declared as input and as a reg type.
build/gpu.v:45: error: Port mem_write_ready of module controller is declared as input and as a reg type.
build/gpu.v:561: error: Port core_done of module dispatch is declared as input and as a reg type.
build/gpu.v:312: warning: input port core_state is coerced to inout.
build/gpu.v:313: warning: input port decoded_alu_arithmetic_mux is coerced to inout.
build/gpu.v:314: warning: input port decoded_alu_output_mux is coerced to inout.
build/gpu.v:315: warning: input port rs is coerced to inout.
build/gpu.v:316: warning: input port rt is coerced to inout.
build/gpu.v:338: warning: input port decoded_mem_read_enable is coerced to inout.
build/gpu.v:339: warning: input port decoded_mem_write_enable is coerced to inout.
build/gpu.v:342: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:343: warning: input port mem_read_data is coerced to inout.
build/gpu.v:347: warning: input port mem_write_ready is coerced to inout.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:369: warning: input port decoded_rd_address is coerced to inout.
build/gpu.v:370: warning: input port decoded_rs_address is coerced to inout.
build/gpu.v:371: warning: input port decoded_rt_address is coerced to inout.
build/gpu.v:367: warning: input port decoded_reg_write_enable is coerced to inout.
build/gpu.v:368: warning: input port decoded_reg_input_mux is coerced to inout.
build/gpu.v:372: warning: input port decoded_immediate is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:374: warning: input port lsu_out is coerced to inout.
build/gpu.v:386: warning: input port decoded_nzp is coerced to inout.
build/gpu.v:388: warning: input port decoded_nzp_write_enable is coerced to inout.
build/gpu.v:389: warning: input port decoded_pc_mux is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:391: warning: input port current_pc is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:234: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:235: warning: input port mem_read_data is coerced to inout.
build/gpu.v:271: warning: input port instruction is coerced to inout.
build/gpu.v:299: warning: input port decoded_ret is coerced to inout.
build/gpu.v:295: warning: input port fetcher_state is coerced to inout.
build/gpu.v:300: warning: input port lsu_state is coerced to inout.
build/gpu.v:302: warning: input port next_pc is coerced to inout.
build/gpu.v:221: error: fetcher_state Unable to assign to unresolved wires.
build/gpu.v:223: error: instruction Unable to assign to unresolved wires.
build/gpu.v:240: error: decoded_rd_address Unable to assign to unresolved wires.
build/gpu.v:242: error: decoded_rs_address Unable to assign to unresolved wires.
build/gpu.v:244: error: decoded_rt_address Unable to assign to unresolved wires.
build/gpu.v:246: error: decoded_nzp Unable to assign to unresolved wires.
build/gpu.v:248: error: decoded_immediate Unable to assign to unresolved wires.
build/gpu.v:250: error: decoded_reg_write_enable Unable to assign to unresolved wires.
build/gpu.v:252: error: decoded_mem_read_enable Unable to assign to unresolved wires.
build/gpu.v:254: error: decoded_mem_write_enable Unable to assign to unresolved wires.
build/gpu.v:256: error: decoded_nzp_write_enable Unable to assign to unresolved wires.
build/gpu.v:258: error: decoded_reg_input_mux Unable to assign to unresolved wires.
build/gpu.v:260: error: decoded_alu_arithmetic_mux Unable to assign to unresolved wires.
build/gpu.v:262: error: decoded_alu_output_mux Unable to assign to unresolved wires.
build/gpu.v:264: error: decoded_pc_mux Unable to assign to unresolved wires.
build/gpu.v:266: error: decoded_ret Unable to assign to unresolved wires.
build/gpu.v:288: error: core_state Unable to assign to unresolved wires.
build/gpu.v:290: error: current_pc Unable to assign to unresolved wires.
build/gpu.v:880: warning: input port block_id is coerced to inout.
build/gpu.v:884: warning: input port program_mem_read_ready is coerced to inout.
build/gpu.v:885: warning: input port program_mem_read_data is coerced to inout.
build/gpu.v:312: warning: input port core_state is coerced to inout.
build/gpu.v:313: warning: input port decoded_alu_arithmetic_mux is coerced to inout.
build/gpu.v:314: warning: input port decoded_alu_output_mux is coerced to inout.
build/gpu.v:315: warning: input port rs is coerced to inout.
build/gpu.v:316: warning: input port rt is coerced to inout.
build/gpu.v:338: warning: input port decoded_mem_read_enable is coerced to inout.
build/gpu.v:339: warning: input port decoded_mem_write_enable is coerced to inout.
build/gpu.v:342: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:343: warning: input port mem_read_data is coerced to inout.
build/gpu.v:347: warning: input port mem_write_ready is coerced to inout.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:369: warning: input port decoded_rd_address is coerced to inout.
build/gpu.v:370: warning: input port decoded_rs_address is coerced to inout.
build/gpu.v:371: warning: input port decoded_rt_address is coerced to inout.
build/gpu.v:367: warning: input port decoded_reg_write_enable is coerced to inout.
build/gpu.v:368: warning: input port decoded_reg_input_mux is coerced to inout.
build/gpu.v:372: warning: input port decoded_immediate is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:374: warning: input port lsu_out is coerced to inout.
build/gpu.v:386: warning: input port decoded_nzp is coerced to inout.
build/gpu.v:388: warning: input port decoded_nzp_write_enable is coerced to inout.
build/gpu.v:389: warning: input port decoded_pc_mux is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:391: warning: input port current_pc is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:365: warning: input port block_id is coerced to inout.
build/gpu.v:373: warning: input port alu_out is coerced to inout.
build/gpu.v:390: warning: input port alu_out is coerced to inout.
build/gpu.v:332: error: Unable to assign words of unresolved wire array.
build/gpu.v:354: error: Unable to assign words of unresolved wire array.
build/gpu.v:356: error: Unable to assign words of unresolved wire array.
build/gpu.v:234: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:235: warning: input port mem_read_data is coerced to inout.
build/gpu.v:271: warning: input port instruction is coerced to inout.
build/gpu.v:299: warning: input port decoded_ret is coerced to inout.
build/gpu.v:295: warning: input port fetcher_state is coerced to inout.
build/gpu.v:300: warning: input port lsu_state is coerced to inout.
build/gpu.v:302: warning: input port next_pc is coerced to inout.
build/gpu.v:221: error: fetcher_state Unable to assign to unresolved wires.
build/gpu.v:223: error: instruction Unable to assign to unresolved wires.
build/gpu.v:240: error: decoded_rd_address Unable to assign to unresolved wires.
build/gpu.v:242: error: decoded_rs_address Unable to assign to unresolved wires.
build/gpu.v:244: error: decoded_rt_address Unable to assign to unresolved wires.
build/gpu.v:246: error: decoded_nzp Unable to assign to unresolved wires.
build/gpu.v:248: error: decoded_immediate Unable to assign to unresolved wires.
build/gpu.v:250: error: decoded_reg_write_enable Unable to assign to unresolved wires.
build/gpu.v:252: error: decoded_mem_read_enable Unable to assign to unresolved wires.
build/gpu.v:254: error: decoded_mem_write_enable Unable to assign to unresolved wires.
build/gpu.v:256: error: decoded_nzp_write_enable Unable to assign to unresolved wires.
build/gpu.v:258: error: decoded_reg_input_mux Unable to assign to unresolved wires.
build/gpu.v:260: error: decoded_alu_arithmetic_mux Unable to assign to unresolved wires.
build/gpu.v:262: error: decoded_alu_output_mux Unable to assign to unresolved wires.
build/gpu.v:264: error: decoded_pc_mux Unable to assign to unresolved wires.
build/gpu.v:266: error: decoded_ret Unable to assign to unresolved wires.
build/gpu.v:288: error: core_state Unable to assign to unresolved wires.
build/gpu.v:290: error: current_pc Unable to assign to unresolved wires.
build/gpu.v:766: warning: input port consumer_read_valid is coerced to inout.
build/gpu.v:767: warning: input port consumer_read_address is coerced to inout.
build/gpu.v:770: warning: input port consumer_write_valid is coerced to inout.
build/gpu.v:771: warning: input port consumer_write_address is coerced to inout.
build/gpu.v:772: warning: input port consumer_write_data is coerced to inout.
build/gpu.v:776: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:777: warning: input port mem_read_data is coerced to inout.
build/gpu.v:781: warning: input port mem_write_ready is coerced to inout.
build/gpu.v:796: warning: input port consumer_read_valid is coerced to inout.
build/gpu.v:797: warning: input port consumer_read_address is coerced to inout.
build/gpu.v:802: warning: input port mem_read_ready is coerced to inout.
build/gpu.v:803: warning: input port mem_read_data is coerced to inout.
build/gpu.v:821: warning: input port core_done is coerced to inout.
build/gpu.v:784: error: fetcher_read_ready Unable to assign to unresolved wires.
build/gpu.v:786: error: fetcher_read_data Unable to assign to unresolved wires.
build/gpu.v:810: error: core_block_id Unable to assign to unresolved wires.
Elaboration failed
make: *** [Makefile:7: test_matadd] Error 1

[troore]

The code in this repo contains very basic verilog/systemverilog syntax errors. I wonder whether the contributors have used some fancy syntax auto-fixing tools.

[adam-maj]

@troore Might just be using a newer version of SV than what you're system is using

[xiyunanhai1995]

@adam-maj
I encountered the same problem.
My system information is as follows:
MacBook Air M1 2020, MacOs 12.7.1
python: 3.10.2
Icarus Verilog: 11.0 (stable)
cocotb: 1.8.1
sv2v: v0.0.11-0-g6082cae
GNU make: 3.81
Which software of mine needs to be updated? could you list your software version.
Do XCode also need to be installed?
Looking forward to your reply very much, thank you.

[peilin-chen]

I also meet the same errors as JunChi1022. But I have solved this problem. The reason for this problem is that some systemverilog files in src folder have syntax errors. After correcting these errors in the files, I run the simulation successfully.

[adviyer]

Do you have the -g2012 flag in your Makefile? That should fix these issues by using a later version of SV instead of the default 2005

[JunChi1022]

Do you have the -g2012 flag in your Makefile? That should fix these issues by using a later version of SV instead of the default 2005

Yes, I have already pull the latest patch. I think i have met the problem same as: #13

[JunChi1022]

I also meet the same errors as JunChi1022. But I have solved this problem. The reason for this problem is that some systemverilog files in src folder have syntax errors. After correcting these errors in the files, I run the simulation successfully.

Did you modify the input reg to input wire?

[peilin-chen]

I also meet the same errors as JunChi1022. But I have solved this problem. The reason for this problem is that some systemverilog files in src folder have syntax errors. After correcting these errors in the files, I run the simulation successfully.

Did you modify the input reg to input wire?

Yes.

[troore]

Do you have the -g2012 flag in your Makefile? That should fix these issues by using a later version of SV instead of the default 2005

@adviyer I don't think -g2012 can fix this issue. It is a basic verilog issue as the input of iverilog in the Makefile is .v rather than .sv. I don't remember in any history version of verilog, reg is allowed for input.

Besides, there are other errors which may cause other simulation tool fails (iverilog may succeed).

[adam-maj]

Will look into this one. Probably my use of SV/2012 syntax is breaking things in many places for people using older versions of any software.

Curious why it's working for some and not for others - my guess is people are using different downloads for iverilog/other tools - if so will update readme with proper links.