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关于在 Verilog TestBench 中运行测试用例 #49

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saltanat3k opened this issue Nov 1, 2020 · 1 comment
Open

关于在 Verilog TestBench 中运行测试用例 #49

saltanat3k opened this issue Nov 1, 2020 · 1 comment

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@saltanat3k
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你好, 我想用你们提供教材里的步骤在ubuntu上进行测试, 但是在 make run_test 的时候没有编译成功。不知道怎么解决,希望能够得到帮助。 本人Linux 新手。

ubuntu

@jasonlee1001
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Makefile 開頭加上:
SHELL := /bin/bash

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